Computer technology has advanced to a point wherein hierarchical systems are quite common. Representative systems consist of modules such as processors, memories, multiplexers and peripheral units, not only represented by a variety of different types, but also with a wide selection of admixtures. Thus, in the same system, a plurality of processors may separately require and control communication with a number of memory units and other peripherals comprising different magnetic and paper tape units, disk and drum magnetic data storage units, and magnetic core stacks, and each may be burdended by constraints which makes its operation different from not only those of the others, but from the processors' as well. A well-known example is temporal operation, i.e., the "clock" rates of the memories are much slower than those of the processors and their time of response to a processor request for information greatly exceeds the time required for the latter to manipulate the information.
Processors in conventional computer systems operate sequentially, i.e., a processor requests access to data in a memory and awaits transfer thereof before submitting another request. However, in the case of plural processors and plural memories, a simple serial activity is economically intolerable, i.e., it is not feasible to deny the recognition of a request from one processor to an idle and available memory merely because another processor is engaged in a data transfer with another memory.
An approach to reducing the contention among independently operating processors in hierarchical systems has been based on the development of a parallelism in which different processors perform simultaneous accesses with different memories by means of intermediate crosspoint switching units. Such units provide independent, controllable interconnection paths between processors and memories, but the units are large and expensive. The present invention discloses a far simpler, though less comprehensive, means to provide concurrency rather than simultaneity in accesses.